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» Combining optimizations in automated low power design
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IPCCC
2006
IEEE
15 years 3 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
DAC
2006
ACM
15 years 10 months ago
An efficient and versatile scheduling algorithm based on SDC formulation
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
Jason Cong, Zhiru Zhang
MOBICOM
2009
ACM
15 years 4 months ago
Dynamic spectrum access in DTV whitespaces: design rules, architecture and algorithms
In November 2008, the FCC ruled that the digital TV whitespaces be used for unlicensed access. This is an exciting development because DTV whitespaces are in the low frequency ran...
Supratim Deb, Vikram Srinivasan, Ritesh Maheshwari
FAABS
2000
Springer
15 years 1 months ago
Design and Mathematical Analysis of Agent-Based Systems
Abstract. Agent-based systems that are composed of simple locally interacting agents but which demonstrate complex group behavior o er several advantages over traditional multi-age...
Kristina Lerman
GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
15 years 3 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...