838 search results - page 128 / 168 » Combining optimizations in automated low power design |
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
In a behavioral synthesis system, a typical approach used to guide the scheduler is to impose hard constraints on the relative timing between operations considering performance, a...
MICRO
2002
IEEE
15 years 2 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
TCAD
2010
14 years 4 months ago
2010
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
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NOCS
2008
IEEE
15 years 4 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...