838 search results - page 132 / 168 » Combining optimizations in automated low power design |
DAC
2009
ACM
15 years 10 months ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
ISCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
ISCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
QOSA
2010
Springer
14 years 7 months ago
2010
Springer
Design decisions for complex, component-based systems impact multiple quality of service (QoS) properties. Often, means to improve one quality property deteriorate another one. In ...
VEE
2009
ACM
15 years 4 months ago
2009
ACM
Clusters provide powerful computing environments, but in practice much of this power goes to waste, due to the static allocation of tasks to nodes, regardless of their changing co...