Sciweavers

838 search results - page 14 / 168
» Combining optimizations in automated low power design
Sort
View
VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
15 years 3 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
DAC
1997
ACM
15 years 3 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
15 years 5 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber
89
Voted
ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
15 years 5 months ago
ILP-based optimization of sequential circuits for low power
The power consumption of a sequential circuit can be reduced by decomposing it into subcircuits which can be turned off when inactive. Power can also be reduced by careful state e...
Feng Gao, John P. Hayes