838 search results - page 16 / 168 » Combining optimizations in automated low power design |
ISLPED
1995
ACM
15 years 1 months ago
1995
ACM
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
88
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as ”Under a timing constraint, to minimize power as much as possible”. Pr...
GLVLSI
2008
IEEE
2008
IEEE
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
14 years 9 months ago
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...
DFT
1999
IEEE
15 years 1 months ago
1999
IEEE
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...