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» Combining optimizations in automated low power design
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MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
15 years 2 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...
SAMOS
2007
Springer
15 years 3 months ago
A Study of Energy Saving in Customizable Processors
Abstract. Embedded systems are special purpose systems which perform predefined tasks with very specific requirements like high performance, low volume or low power. Most of the ...
Paolo Bonzini, Dilek Harmanci, Laura Pozzi
73
Voted
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
15 years 6 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
CSREAESA
2004
14 years 11 months ago
Survey and Evaluation of Low-Power Full-Adder Cells
In this paper, we survey various designs of low-power full-adder cells from conventional CMOS to really inventive XOR-based designs. We further describe simulation experiments tha...
Ahmed Sayed, Hussain Al-Asaad
CASES
2000
ACM
15 years 2 months ago
A first-step towards an architecture tuning methodology for low power
We describe an automated environment to assist a system-on-achip designer to tune a microprocessor core to a particular application program that will run on the microprocessor, an...
Greg Stitt, Frank Vahid, Tony Givargis, Roman L. L...