838 search results - page 19 / 168 » Combining optimizations in automated low power design |
ATS
1997
IEEE
15 years 1 months ago
1997
IEEE
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
DAC
1998
ACM
15 years 10 months ago
1998
ACM
DAC
1999
ACM
15 years 10 months ago
1999
ACM
We present a novel approach that minimizes the power consumption of embedded core-based systems through hardware/software partitioning. Our approach is based on the idea of mapping...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
In 90-nm technology, dynamic power is still the largest power source in FPGAs [1], and signal glitches contribute a large portion of the dynamic power consumption. Previous powera...
59
Voted
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...