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» Combining optimizations in automated low power design
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GLOBECOM
2009
IEEE
15 years 4 months ago
Joint Power Control and Beamforming Codebook Design for MISO Channels with Limited Feedback
Abstract— This paper investigates the joint design and optimization of the power control and beamforming codebooks for the single-user multiple-input single-output (MISO) wireles...
Behrouz Khoshnevis, Wei Yu
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
15 years 3 months ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
84
Voted
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 2 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
66
Voted
DSD
2004
IEEE
104views Hardware» more  DSD 2004»
15 years 1 months ago
A Static Low-Power, High-Performance 32-bit Carry Skip Adder
In this paper, we present a full-static carry-skip adder designed to achieve low power dissipation and high-performance operation. To reduce the adder's delay and power consu...
Kai Chirca, Michael J. Schulte, John Glossner, Hao...
60
Voted
ISCAS
2007
IEEE
149views Hardware» more  ISCAS 2007»
15 years 4 months ago
Compact, Low Power Wireless Sensor Network System for Line Crossing Recognition
— Many application-specific wireless sensor network (WSN) systems require small size and low power features due to their limited resources, and their use in distributed, wireles...
Chung-Ching Shen, Roni Kupershtok, Bo Yang, Felice...