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» Combining optimizations in automated low power design
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DAC
2005
ACM
15 years 10 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ADHOCNOW
2004
Springer
15 years 3 months ago
A Rate-Adaptive MAC Protocol for Low-Power Ultra-Wide Band Ad-Hoc Networks
Recent theoretical results show that it is optimal to allow interfering sources to transmit simultaneously as long as they are outside a well-defined exclusion region around a de...
Ruben Merz, Jean-Yves Le Boudec, Jörg Widmer,...
83
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GLOBECOM
2007
IEEE
14 years 11 months ago
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation
: The improvement of spectral efficiency comes at the cost of exponential increment of signal processing complexity [1]. Hence, the energy-efficiency of baseband has recently turne...
Min Li, Bruno Bougard, Eduardo Lopez-Estraviz, And...
SAMOS
2007
Springer
15 years 3 months ago
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
Pepijn J. de Langen, Ben H. H. Juurlink
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
15 years 4 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...