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» Combining optimizations in automated low power design
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82
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DAC
2006
ACM
15 years 10 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
CSE
2009
IEEE
15 years 1 months ago
Rotation Scheduling and Voltage Assignment to Minimize Energy for SoC
— Low energy consumption is a critical issue in embedded systems design. As the technology feature sizes of SoC (Systems on Chip) become smaller and smaller, the percentage of le...
Meikang Qiu, Laurence Tianruo Yang, Edwin Hsing-Me...
90
Voted
CORR
2010
Springer
122views Education» more  CORR 2010»
14 years 9 months ago
Optimum Power and Rate Allocation for Coded V-BLAST: Average Optimization
An analytical framework for performance analysis and optimization of coded V-BLAST is developed. Average power and/or rate allocations to minimize the outage probability as well as...
Victoria Kostina, Sergey Loyka
85
Voted
SBCCI
2009
ACM
187views VLSI» more  SBCCI 2009»
15 years 2 months ago
Design of low complexity digital FIR filters
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
Levent Aksoy, Diego Jaccottet, Eduardo Costa
88
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AAAI
2007
15 years 13 hour ago
Automated Online Mechanism Design and Prophet Inequalities
Recent work on online auctions for digital goods has explored the role of optimal stopping theory — particularly secretary problems — in the design of approximately optimal on...
Mohammad Taghi Hajiaghayi, Robert D. Kleinberg, Tu...