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» Combining optimizations in automated low power design
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74
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FPGA
2004
ACM
136views FPGA» more  FPGA 2004»
15 years 3 months ago
Active leakage power optimization for FPGAs
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
Jason Helge Anderson, Farid N. Najm, Tim Tuan
88
Voted
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
15 years 6 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He
DAC
2002
ACM
15 years 10 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid
TVLSI
2002
104views more  TVLSI 2002»
14 years 9 months ago
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
This paper compares four previously published static dual-edge-triggered flip-flops (DETFFs) with a proposed design for their performance, power dissipation, and low-voltage low-po...
Wai Chung, Timothy Lo, Manoj Sachdev
IROS
2006
IEEE
138views Robotics» more  IROS 2006»
15 years 3 months ago
Power Electronics Design Choice for Piezoelectric Microrobots
Abstract— Piezoelectric actuators are advantageous for microrobots due to their light weight, high bandwidth, high force production, low power consumption, and simplicity of inte...
Erik Steltz, M. Seeman, Srinath Avadhanula, Ronald...