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» Combining optimizations in automated low power design
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CODES
2006
IEEE
15 years 3 months ago
Layout aware design of mesh based NoC architectures
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
Krishnan Srinivasan, Karam S. Chatha
QSIC
2007
IEEE
15 years 4 months ago
Synthesizing Component-Based WSN Applications via Automatic Combination of Code Optimization Techniques
Wireless sensor network (WSN) applications sense events in-situ and compute results in-network. Their software components should run on platforms with stringent constraints on nod...
Zhenyu Zhang, W. K. Chan, T. H. Tse
CODES
2005
IEEE
15 years 3 months ago
System-level design automation tools for digital microfluidic biochips
Biochips based on digital microfluidics offer a powerful platform for massively parallel biochemical analysis such as clinical diagnosis and DNA sequencing. Current full-custom de...
Krishnendu Chakrabarty, Fei Su
DAC
2008
ACM
15 years 10 months ago
A power and temperature aware DRAM architecture
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temper...
Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Mem...
DATE
1999
IEEE
129views Hardware» more  DATE 1999»
15 years 2 months ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu