838 search results - page 49 / 168 » Combining optimizations in automated low power design |
DAC
2005
ACM
15 years 10 months ago
2005
ACM
This paper presents the first in-depth study on applying dual Vdd buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constrai...
ICC
2008
IEEE
15 years 4 months ago
2008
IEEE
—This paper addresses the joint estimator and power optimization problem for a sensor network whose mission is to estimate an unknown parameter. We assume a two-hop network where...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
IPSN
2009
Springer
15 years 4 months ago
2009
Springer
As the diversity of sensornet use cases increases, the combinations of environments and applications that will coexist will make custom engineering increasingly impractical. We in...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we present two polynomial time-complexity heuristic algorithms for optimization of gate-oxide leakage (tunneling current) during behavioral synthesis through simulta...