838 search results - page 51 / 168 » Combining optimizations in automated low power design |
DSD
2005
IEEE
15 years 3 months ago
2005
IEEE
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
SECON
2007
IEEE
2007
IEEE
Experimental Investigation of IEEE 802.15.4 Transmission Power Control and Interference Minimization
15 years 4 months ago
Abstract—Although the characteristics of RF transmissions are physically well understood at the lowest levels of communication design, accurately incorporating power and interfer...
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
ISLPED
2003
ACM
15 years 3 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...