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» Combining optimizations in automated low power design
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ASPDAC
2001
ACM
83views Hardware» more  ASPDAC 2001»
15 years 1 months ago
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
Tony Givargis, Frank Vahid, Jörg Henkel
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
15 years 1 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram
ANCS
2009
ACM
14 years 7 months ago
Design of a scalable nanophotonic interconnect for future multicores
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
Avinash Karanth Kodi, Randy Morris
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
15 years 3 months ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
WEBI
2007
Springer
15 years 3 months ago
Improving Performance of Web Services Query Matchmaking with Automated Knowledge Acquisition
There is a critical need to design and develop tools tract away the fundamental complexity of XML-based Web services specifications and toolkits, and provide an elegant, intuitive...
Chaitali Gupta, Rajdeep Bhowmik, Michael R. Head, ...