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» Combining optimizations in automated low power design
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ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
15 years 6 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
DATE
2010
IEEE
118views Hardware» more  DATE 2010»
14 years 8 months ago
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Minje Jun, Sungroh Yoon, Eui-Young Chung
DAC
2000
ACM
15 years 10 months ago
Power analysis of embedded operating systems
The increasing complexity and software content of embedded systems has led to the common use of sophisticated system software that helps applications use the underlying hardware r...
Robert P. Dick, Ganesh Lakshminarayana, Anand Ragh...
GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
15 years 3 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
GLOBECOM
2007
IEEE
15 years 4 months ago
MIMO-OFDM Channel Estimation in Presence of Carrier Frequency Offsets
— Optimal pilot design and placement for channel estimation in Multiple-input Multiple-output (MIMO) Orthogonal Frequency-Division Multiplexing (OFDM) systems in the presence of ...
Zhongshan Zhang, Wei Zhang, Chintha Tellambura