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» Combining optimizations in automated low power design
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VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
15 years 10 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
DAC
2001
ACM
15 years 10 months ago
Dynamic Voltage Scaling and Power Management for Portable Systems
Portable systems require long battery lifetime while still delivering high performance. Dynamic voltage scaling (DVS) algorithms reduce energy consumption by changing processor sp...
Tajana Simunic, Luca Benini, Andrea Acquaviva, Pet...
GECCO
2006
Springer
253views Optimization» more  GECCO 2006»
15 years 1 months ago
A novel approach to optimize clone refactoring activity
Achieving a high quality and cost-effective tests is a major concern for software buyers and sellers. Using tools and integrating techniques to carry out low cost testing are chal...
Salah Bouktif, Giuliano Antoniol, Ettore Merlo, Ma...
DAC
2005
ACM
15 years 10 months ago
Variations-aware low-power design with voltage scaling
We present a new methodology which takes into consideration the effect of Within-Die (WID) process variations on a low-voltage parallel system. We show that in the presence of pro...
Navid Azizi, Muhammad M. Khellah, Vivek De, Farid ...
DAC
2004
ACM
15 years 1 months ago
Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...
R. Reed Taylor, Herman Schmit