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» Combining optimizations in automated low power design
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SIGCOMM
2010
ACM
14 years 10 months ago
NapSAC: design and implementation of a power-proportional web cluster
Energy consumption is a major and costly problem in data centers. A large fraction of this energy goes to powering idle machines that are not doing any useful work. We identify tw...
Andrew Krioukov, Prashanth Mohan, Sara Alspaugh, L...
HPCA
2009
IEEE
15 years 10 months ago
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...
Niti Madan, Li Zhao, Naveen Muralimanohar, Anirudd...
IEEEPACT
2006
IEEE
15 years 3 months ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
TVLSI
2008
139views more  TVLSI 2008»
14 years 9 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
14 years 11 months ago
Power estimation starategies for a low-power security processor
In this paper, we present the power estimation methodologies for the development of a low-power security processor that contains significant amount of logic and memory. For the lo...
Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling C...