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ISCAS
2005
IEEE
143views Hardware» more  ISCAS 2005»
15 years 11 months ago
Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation
— In this paper, we design and implement an improved hardware-based evolutionary digital filter (EDF) version 2. The EDF is an adaptive digital filter which is controlled by ad...
Masahide Abe, Hiroki Arai, Masayuki Kawamata
ISCAS
2005
IEEE
124views Hardware» more  ISCAS 2005»
15 years 11 months ago
One-pass computation-aware motion estimation with adaptive search strategy
— A computation-aware motion estimation algorithm is proposed in this paper. Its goal is to find the best block matching results in a computation-limited and computation-variant...
Yu-Wen Huang, Chia-Lin Lee, Ching-Yeh Chen, Liang-...
ISCAS
2005
IEEE
122views Hardware» more  ISCAS 2005»
15 years 11 months ago
A mixed analog-digital hybrid for speech enhancement purposes
Abstract— This paper presents and evaluates a hybrid implementation of a low complexity algorithm for speech enhancement, the Adaptive Gain Equalizer (AGE). The AGE is a subband ...
Benny Sallberg, Mattias Dahl, Henrik Akesson, Ingv...
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
15 years 11 months ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...
ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
15 years 11 months ago
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
Hao Yu, Lei He
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