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ASPDAC
2006
ACM
133views Hardware» more  ASPDAC 2006»
15 years 7 months ago
An SPU reference model for simulation, random test generation and verification
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
Yukio Watanabe, Balazs Sallay, Brad W. Michael, Da...
TII
2008
109views more  TII 2008»
15 years 1 months ago
Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels
This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The pr...
Kyung Ki Kim, Jing Huang, Yong-Bin Kim, Fabrizio L...
109
Voted
COMPSAC
2008
IEEE
15 years 2 months ago
Superfit Combinational Elusive Bug Detection
Software that has been well tested and analyzed may fail unpredictably when a certain combination of conditions occurs. In Bounded Exhaustive Testing (BET) all combinations are te...
R. Barzin, S. Fukushima, William E. Howden, S. Sha...
98
Voted
ATAL
2008
Springer
15 years 3 months ago
Ontology-based test generation for multiagent systems
This paper investigates software agents testing, and in particular how to automate test generation. We propose a novel approach, which takes advantage of agent interaction ontolog...
Duy Cu Nguyen, Anna Perini, Paolo Tonella
JAVACARD
2000
15 years 5 months ago
Automatic Test Generation for Java-Card Applets
: Open-cards have introduced a new life cycle for smart card embedded applications. In the case of Java Card, they have raised the problem of embedded object-oriented applet valida...
Hugues Martin, Lydie du Bousquet