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ISCA
2002
IEEE
95views Hardware» more  ISCA 2002»
15 years 8 months ago
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
Ho-Seop Kim, James E. Smith
CDC
2010
IEEE
100views Control Systems» more  CDC 2010»
14 years 10 months ago
Impulsive systems triggered by superposed renewal processes
We consider impulsive systems with several reset maps triggered by independent renewal processes, i.e., the intervals between jumps associated with a given reset map are identicall...
Duarte Antunes, João Pedro Hespanha, Carlos...
IJFCS
2006
82views more  IJFCS 2006»
15 years 3 months ago
Routing Multiple Width Communications on the Circuit Switched Tree
Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such ar...
Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L...
FPL
2005
Springer
130views Hardware» more  FPL 2005»
15 years 8 months ago
Communication Synthesis in a multiprocessor environment
At Leiden University, we are developing a design methodology that allows for fast mapping of nested-loop applications (e.g. DSP, Imaging, or MultiMedia) written in a subset of Matl...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
AGENTCL
2003
Springer
15 years 8 months ago
An Empirical Model of Communication in Multiagent Systems
Abstract. This paper proposes a new model of communication in multiagent systems according to which the semantics of communication depends on their pragmatics. Since these pragmati...
Michael Rovatsos, Matthias Nickles, Gerhard Wei&sz...