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ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
15 years 5 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
EDBT
2008
ACM
159views Database» more  EDBT 2008»
15 years 12 months ago
P2P systems with transactional semantics
Structured P2P systems have been developed for constructing applications at internet scale in cooperative environments and exhibit a number of desirable features such as scalabili...
Shyam Antony, Divyakant Agrawal, Amr El Abbadi
INTERACT
2003
15 years 1 months ago
Creating New User Experiences to Enhance Collaboration
: When technologies are introduced into collaborative settings, people are often required to work together in new, unfamiliar ways. This can lead to problems of resistance, and eve...
John Halloran, Yvonne Rogers, Tom Rodden, Ian Tayl...
ACISP
1998
Springer
15 years 4 months ago
LITESET: A Light-Weight Secure Electronic Transaction Protocol
Abstract. The past few years have seen the emergence of a large number of proposals for electronic payments over open networks. Among these proposals is the Secure Electronic Trans...
Goichiro Hanaoka, Yuliang Zheng, Hideki Imai
CAL
2008
14 years 10 months ago
Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. Howev...
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, ...