362 search results - page 46 / 73 » Communication Mechanisms for Parallel DSP Systems on a Chip |
131
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ICS
2010
Tsinghua U.
15 years 2 months ago
2010
Tsinghua U.
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
131
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PPOPP
2003
ACM
15 years 5 months ago
2003
ACM
A design pattern is a mechanism for encapsulating the knowledge of experienced designers into a re-usable artifact. Parallel design patterns reflect commonly occurring parallel co...
107
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HPCN
1998
Springer
15 years 4 months ago
1998
Springer
We describe the Paraflow system for connecting heterogeneous computing services together into a flexible and efficient data-mining metacomputer. There are three levels of parallel...
113
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ASAP
2008
IEEE
15 years 6 months ago
2008
IEEE
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
ASAP
2007
IEEE
14 years 12 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...