As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
In this paper we study the problem of scheduling messages between two parallel machines connected by a low latency network during a data redistribution. We compare two approaches....
Abstract— The design of LDPC decoders with low complexity, high throughput, and good performance is a critical task. A well-known strategy is to design structured codes such as q...
Yuan-Mao Chang, Andres I. Vila Casado, Mau-Chung F...
Air pollution, traffic congestion, stress and accidents are common features of today’s road transportation experience. New approaches to improving the efficiency and safety of t...
Vinny Cahill, Aline Senart, Douglas C. Schmidt, St...
— In this paper, we study cross-layer design for rate control in multihop wireless networks. In our previous work, we have developed an optimal cross-layered rate control scheme ...