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ARC
2010
Springer
183views Hardware» more  ARC 2010»
15 years 5 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
133
Voted
CCS
2010
ACM
15 years 5 months ago
CRAFT: a new secure congestion control architecture
Congestion control algorithms seek to optimally utilize network resources by allocating a certain rate for each user. However, malicious clients can disregard the congestion contr...
Dongho Kim, Jerry T. Chiang, Yih-Chun Hu, Adrian P...
CCS
2010
ACM
15 years 5 months ago
Secure latency estimation with treeple
A network latency estimation scheme associates a "position" to every peer in a distributed network such that the latency between any two nodes can be accurately estimate...
Eric Chan-Tin, Nicholas Hopper
ICASSP
2010
IEEE
15 years 5 months ago
Buffer management for multi-application image processing on multi-core platforms: Analysis and case study
Due to the limited amounts of on-chip memory, large volumes of data, and performance and power consumption overhead associated with interprocessor communication, efficient managem...
Dong-Ik Ko, Nara Won, Shuvra S. Bhattacharyya
152
Voted
TEI
2010
ACM
129views Hardware» more  TEI 2010»
15 years 5 months ago
Silent mutations: physical-digital interactions in spaces
Many installations research efforts today explore how to engage participants with embedded digital content and applications in interactive environments. Yet the interactive design...
Claudia Rébola Winegarden, Nicholas Komor, ...
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