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DAC
2009
ACM
15 years 10 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
APCSAC
2006
IEEE
15 years 3 months ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
107
Voted
SIGMETRICS
2003
ACM
165views Hardware» more  SIGMETRICS 2003»
15 years 2 months ago
A hybrid systems modeling framework for fast and accurate simulation of data communication networks
In this paper we present a general hybrid systems modeling framework to describe the flow of traffic in communication networks. To characterize network behavior, these models use...
Stephan Bohacek, João P. Hespanha, Junsoo L...
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 1 months ago
Hardware Synthesis from C/C++ Models
Software programming languages, such as C/C++, have been used as means for specifying hardware for quite a while. Different design methodologies have exploited the advantages of f...
Giovanni De Micheli
TNN
2008
138views more  TNN 2008»
14 years 9 months ago
A Fast and Scalable Recurrent Neural Network Based on Stochastic Meta Descent
This brief presents an efficient and scalable online learning algorithm for recurrent neural networks (RNNs). The approach is based on the real-time recurrent learning (RTRL) algor...
Zhenzhen Liu, Itamar Elhanany