14007 search results - page 10 / 2802 » Communications in Bus Networks |
NOCS
2009
IEEE
15 years 4 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
ASPDAC
2006
ACM
15 years 4 months ago
2006
ACM
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
HPCA
1998
IEEE
15 years 2 months ago
1998
IEEE
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
ICCAD
1998
IEEE
15 years 2 months ago
1998
IEEE
Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing desi...
ISQED
2006
IEEE
15 years 4 months ago
2006
IEEE
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...