14007 search results - page 138 / 2802 » Communications in Bus Networks |
46
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IPPS
1998
IEEE
15 years 3 months ago
1998
IEEE
Fully-populated tori, where every node has a processor attached, do not scale well since load on edges increases superlinearly with network size under heavy communication, resulti...
111
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CORR
2011
Springer
14 years 6 months ago
2011
Springer
Abstract—This paper addresses combinatorial optimization schemes for solving the multicriteria Steiner tree problem for communication network topology design (e.g., wireless mesh...
ICCD
2002
IEEE
15 years 8 months ago
2002
IEEE
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
ICCAD
2002
IEEE
15 years 8 months ago
2002
IEEE
This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a rec...
ISCAS
2007
IEEE
15 years 5 months ago
2007
IEEE
—Various instruction and transaction based power estimation techniques for processor and on-chip buses have been proposed in the past. In this paper, we propose a heterogeneous p...