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JUCS
2008
153views more  JUCS 2008»
14 years 10 months ago
Bus Network Optimization with a Time-Dependent Hybrid Algorithm
: This paper describes a new hybrid technique that combines a Greedy Randomized Adaptive Search Procedure (GRASP) and a genetic algorithm with simulation features in order to solve...
Ana C. Olivera, Mariano Frutos, Jessica Andrea Car...
DAC
2008
ACM
14 years 12 months ago
Protecting bus-based hardware IP by secret sharing
Our work addresses protection of hardware IP at the mask level with the goal of preventing unauthorized manufacturing. The proposed protocol based on chip locking and activation i...
Jarrod A. Roy, Farinaz Koushanfar, Igor L. Markov
ISICT
2003
14 years 11 months ago
An evolutionary approach for reducing the energy in address buses
In this paper we present a genetic approach for the efficient generation of an encoder to minimize switching activity on the high-capacity lines of a communication bus. The appro...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
JSAC
2007
93views more  JSAC 2007»
14 years 10 months ago
Optimal Virtual Topology Design using Bus-Label Switched Paths
— Although there is a trend in reducing the number of layers in core and metropolitan area networks, still the optimal design of multi-layer networks (like IP over WDM) remains a...
Yannick Brehon, Daniel Kofman, Michal Pióro...
ASPDAC
2008
ACM
94views Hardware» more  ASPDAC 2008»
15 years 2 days ago
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival
A major trend in a modern system-on-chip design is a growing system complexity, which results in a sharp increase of communication traffic on the on-chip communication bus architec...
Sujan Pandey, Rolf Drechsler