14007 search results - page 30 / 2802 » Communications in Bus Networks |
EUROPAR
1997
Springer
15 years 2 months ago
1997
Springer
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to ...
DATE
2006
IEEE
15 years 4 months ago
2006
IEEE
The increasing complexity of embedded systems pushes system designers to higher levels of abstraction. Transaction Level Modeling (TLM) has been proposed to model ation in systems...
ASPDAC
2001
ACM
15 years 1 months ago
2001
ACM
ct,. In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed wire mqd...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
IEEEPACT
1998
IEEE
15 years 2 months ago
1998
IEEE
The fast evolution of processor performance necessitates a permanent evolution of all the multiprocessor components, even for small to medium-scale symmetric multiprocessors (SMP)...