Sciweavers

14007 search results - page 52 / 2802
» Communications in Bus Networks
Sort
View
112
Voted
SIGMETRICS
2012
ACM
271views Hardware» more  SIGMETRICS 2012»
13 years 21 days ago
An empirical comparison of Java remote communication primitives for intra-node data transmission
This paper presents a benchmarking suite that measures the performance of using sockets and eXtensible Markup Language remote procedure calls (XML-RPC) to exchange intra-node mess...
Philip F. Burdette, William F. Jones, Brian C. Blo...
113
Voted
NCA
1998
IEEE
14 years 10 months ago
A Neural Network Model of a Communication Network with Information Servers
This paper models information flow in a communication network. The network consists of nodes that communicate with each other, and information servers that have a predominantly o...
Philippe De Wilde
86
Voted
FPL
2008
Springer
153views Hardware» more  FPL 2008»
14 years 11 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
77
Voted
CODES
2007
IEEE
15 years 4 months ago
Performance and resource optimization of NoC router architecture for master and slave IP cores
System-on-Chip architectures incorporate several IP cores with well defined master and slave characteristics in terms of on-chip communication. The paper presents a parameterized ...
Glenn Leary, Krishna Mehta, Karam S. Chatha
86
Voted
EDCC
1999
Springer
15 years 2 months ago
A Fault Tolerant Clock Synchronization Algorithm for Systems with Low-Precision Oscillators
In this paper we present a new fault tolerant clock synchronization algorithm called the Fault Tolerant Daisy Chain algorithm. It is intended for internal clock synchronization of...
Henrik Lönn