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CHES
2003
Springer
247views Cryptology» more  CHES 2003»
15 years 10 months ago
Very Compact FPGA Implementation of the AES Algorithm
Abstract. In this paper a compact FPGA architecture for the AES algorithm with 128-bit key targeted for low-cost embedded applications is presented. Encryption, decryption and key ...
Pawel Chodowiec, Kris Gaj
ICDAR
2009
IEEE
15 years 2 months ago
Design Compact Recognizers of Handwritten Chinese Characters Using Precision Constrained Gaussian Models, Minimum Classification
In our previous work, a precision constrained Gaussian model (PCGM) was proposed for character modeling to design compact recognizers of handwritten Chinese characters. A maximum ...
Yongqiang Wang, Qiang Huo
WWW
2006
ACM
16 years 5 months ago
XML screamer: an integrated approach to high performance XML parsing, validation and deserialization
This paper describes an experimental system in which customized high performance XML parsers are prepared using parser generation and compilation techniques. Parsing is integrated...
Margaret Gaitatzes Kostoulas, Morris Matsa, Noah M...
ATS
2009
IEEE
111views Hardware» more  ATS 2009»
15 years 11 months ago
Dynamic Compaction in SAT-Based ATPG
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
Alejandro Czutro, Ilia Polian, Piet Engelke, Sudha...
GLOBECOM
2006
IEEE
15 years 11 months ago
Antenna Selection for Compact Dual-Polarized MIMO Systems with Linear Receivers
— Antenna selection combined with dual-polarized antennas offers an attractive alternative for realizing higher order multiple-input multiple-output (MIMO) configurations in com...
Vikram R. Anreddy, Mary Ann Ingram