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DATE
2008
IEEE
116views Hardware» more  DATE 2008»
15 years 4 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
BMCBI
2008
99views more  BMCBI 2008»
14 years 10 months ago
Multiple organism algorithm for finding ultraconserved elements
Background: Ultraconserved elements are nucleotide or protein sequences with 100% identity (no mismatches, insertions, or deletions) in the same organism or between two or more or...
Scott Christley, Neil F. Lobo, Gregory R. Madey
DAC
2005
ACM
15 years 10 months ago
Incremental exploration of the combined physical and behavioral design space
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Z...
CCECE
2006
IEEE
15 years 3 months ago
FPGA-Based SAT Solver
Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. We present an FPGA based clause evaluator,...
Mona Safar, M. Watheq El-Kharashi, Ashraf Salem
VIS
2006
IEEE
214views Visualization» more  VIS 2006»
15 years 11 months ago
Hub-based Simulation and Graphics Hardware Accelerated Visualization for Nanotechnology Applications
The Network for Computational Nanotechnology (NCN) has developed a science gateway at nanoHUB.org for nanotechnology education and research. Remote users can browse through online...
Wei Qiao, Michael McLennan, Rick Kennell, David...