20197 search results - page 3387 / 4040 » Comparing Computational Power |
199
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DAC
2008
ACM
16 years 8 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
151
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DAC
2007
ACM
16 years 8 months ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...
248
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DAC
2000
ACM
16 years 8 months ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
201
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DAC
2000
ACM
16 years 8 months ago
2000
ACM
We describe METRICS, a system to recover design productivity via new infrastructure for design process optimization. METRICS seeks to treat system design and implementation as a s...
194
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DAC
2000
ACM
16 years 8 months ago
2000
ACM
This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation based tool th...