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» Comparing Operating Systems Using Robustness Benchmarks
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136
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WSC
2008
15 years 6 months ago
Discrete Rate Simulation using linear programming
Discrete Rate Simulation (DRS) is a modeling methodology that uses event based logic to simulate linear continuous processes and hybrid systems. These systems are concerned with t...
Cecile Damiron, Anthony Nastasi
127
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ICS
1995
Tsinghua U.
15 years 7 months ago
Optimum Modulo Schedules for Minimum Register Requirements
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
Alexandre E. Eichenberger, Edward S. Davidson, San...
115
Voted
ICCAD
2004
IEEE
121views Hardware» more  ICCAD 2004»
16 years 16 days ago
Factoring and eliminating common subexpressions in polynomial expressions
Polynomial expressions are used to compute a wide variety of mathematical functions commonly found in signal processing and graphics applications, which provide good opportunities...
Anup Hosangadi, Farzan Fallah, Ryan Kastner
138
Voted
FPL
2007
Springer
136views Hardware» more  FPL 2007»
15 years 9 months ago
A Load/Store Unit for a Memcpy Hardware Accelerator
Recently, a dedicated hardware accelerator was proposed that works in conjunction with caches found next to modern-day microprocessors, to speedup the commonly utilized memcpy ope...
Stamatis Vassiliadis, Filipa Duarte, Stephan Wong
113
Voted
ICCAD
2000
IEEE
77views Hardware» more  ICCAD 2000»
15 years 8 months ago
Improving the Proportion of At-Speed Tests in Scan BIST
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janus...