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ARCS
2009
Springer
15 years 6 months ago
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
Joseph Gebis, Leonid Oliker, John Shalf, Samuel Wi...
CF
2009
ACM
15 years 6 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
IMC
2009
ACM
15 years 6 months ago
Live streaming performance of the Zattoo network
A number of commercial peer-to-peer systems for live streaming, such as PPLive, Joost, LiveStation, SOPCast, TVants, etc. have been introduced in recent years. The behavior of the...
Hyunseok Chang, Sugih Jamin, Wenjie Wang
SIGGRAPH
2009
ACM
15 years 6 months ago
RACBVHs: random-accessible compressed bounding volume hierarchies
We present a novel bounding volume hierarchy (BVH) compression and decompression method transparently supporting random access on the compressed BVHs. To support random access on ...
Tae-Joon Kim, Bochang Moon, Duksu Kim, Sung-Eui Yo...
CODES
2008
IEEE
15 years 6 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra