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DAC
2007
ACM
16 years 5 months ago
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
DAC
2003
ACM
16 years 5 months ago
On-chip logic minimization
While Boolean logic minimization is typically used in logic synthesis, logic minimization can be useful in numerous other applications. However, many of those applications, such a...
Roman L. Lysecky, Frank Vahid
DAC
2004
ACM
16 years 5 months ago
Dynamic FPGA routing for just-in-time FPGA compilation
Just-in-time (JIT) compilation has previously been used in many applications to enable standard software binaries to execute on different underlying processor architectures. Howev...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
DAC
2006
ACM
16 years 5 months ago
Stochastic variational analysis of large power grids considering intra-die correlations
For statistical timing and power analysis that are very important problems in the sub-100nm technologies, stochastic analysis of power grids that characterizes the voltage fluctua...
Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhar...
IPMI
2005
Springer
16 years 5 months ago
Spherical Navigator Registration Using Harmonic Analysis for Prospective Motion Correction
Spherical navigators are an attractive approach to motion compensation in Magnetic Resonance Imaging. Because they can be acquired quickly, spherical navigators have the potential ...
Christopher L. Wyatt, Narter Ari, Robert A. Kraft
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