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ICCAD
1995
IEEE
88views Hardware» more  ICCAD 1995»
15 years 6 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
230
Voted
CVPR
2010
IEEE
15 years 4 months ago
Simultaneous Searching of Globally Optimal Interacting Surfaces with Shape Priors
Multiple surface searching with only image intensity information is a difficult job in the presence of high noise and weak edges. We present in this paper a novel method for global...
Qi Song, Xiaodong Wu, Yunlong Liu, Mona Garvin, Mi...
ETS
2010
IEEE
174views Hardware» more  ETS 2010»
15 years 3 months ago
Test-architecture optimization for TSV-based 3D stacked ICs
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakr...
122
Voted
TCAD
1998
82views more  TCAD 1998»
15 years 2 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
JGO
2011
89views more  JGO 2011»
14 years 5 months ago
Model building using bi-level optimization
Abstract In many problems from different disciplines such as engineering, physics, medicine, and biology, a series of experimental data is used in order to generate a model that ca...
Georges K. Saharidis, Ioannis P. Androulakis, Mari...