Sciweavers

1654 search results - page 323 / 331
» Comparing Two Software Design Process Theories
Sort
View
SIPS
2008
IEEE
15 years 4 months ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
RTSS
2006
IEEE
15 years 3 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
CASES
2009
ACM
15 years 4 months ago
Fine-grain performance scaling of soft vector processors
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
Peter Yiannacouras, J. Gregory Steffan, Jonathan R...
ASPLOS
1992
ACM
15 years 2 months ago
Parity Declustering for Continuous Operation in Redundant Disk Arrays
We describe and evaluate a strategy for declustering the parity encoding in a redundant disk array. This declustered parity organization balances cost against data reliability and...
Mark Holland, Garth A. Gibson
BMCBI
2008
155views more  BMCBI 2008»
14 years 10 months ago
Extending pathways based on gene lists using InterPro domain signatures
Background: High-throughput technologies like functional screens and gene expression analysis produce extended lists of candidate genes. Gene-Set Enrichment Analysis is a commonly...
Florian Hahne, Alexander Mehrle, Dorit Arlt, Annem...