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» Comparing designs for computer simulation experiments
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147
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ADHOC
2007
135views more  ADHOC 2007»
15 years 3 months ago
Mitigating the gateway bottleneck via transparent cooperative caching in wireless mesh networks
Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congest...
Saumitra M. Das, Himabindu Pucha, Y. Charlie Hu
BMCBI
2006
145views more  BMCBI 2006»
15 years 3 months ago
GEM System: automatic prototyping of cell-wide metabolic pathway models from genomes
Background: Successful realization of a "systems biology" approach to analyzing cells is a grand challenge for our understanding of life. However, current modeling appro...
Kazuharu Arakawa, Yohei Yamada, Kosaku Shinoda, Yo...
HPCA
2009
IEEE
16 years 3 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
15 years 10 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
123
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ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
15 years 1 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen