Sciweavers

288 search results - page 10 / 58
» Comparing memory systems for chip multiprocessors
Sort
View
DAC
2004
ACM
16 years 6 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
DATE
2008
IEEE
130views Hardware» more  DATE 2008»
15 years 7 months ago
A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications
This paper presents the implementation of a dualpriority scheduling algorithm for real-time embedded systems on a shared memory multiprocessor on FPGA. The dual-priority microkern...
Antonino Tumeo, Marco Branca, Lorenzo Camerini, Ma...
TJS
2010
145views more  TJS 2010»
14 years 12 months ago
Analyzing and enhancing the parallel sort operation on multithreaded architectures
The Sort operation is a core part of many critical applications. Despite the large efforts to parallelize it, the fact that it suffers from high data-dependencies vastly limits it...
Layali K. Rashid, Wessam Hassanein, Moustafa A. Ha...
TPDS
2010
260views more  TPDS 2010»
15 years 3 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear
VLDB
2001
ACM
149views Database» more  VLDB 2001»
15 years 9 months ago
Cache-Conscious Concurrency Control of Main-Memory Indexes on Shared-Memory Multiprocessor Systems
Recent research addressed the importance of optimizing L2 cache utilization in the design of main memory indexes and proposed the so-called cache-conscious indexes such as the CSB...
Sang Kyun Cha, Sangyong Hwang, Kihong Kim, Keunjoo...