Sciweavers

288 search results - page 11 / 58
» Comparing memory systems for chip multiprocessors
Sort
View
ISSS
2002
IEEE
126views Hardware» more  ISSS 2002»
15 years 2 months ago
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design
In this paper, we present a new methodology for application specific multiprocessor system-on-chip design. This approach facilitates the integration of existing components with th...
Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali...
EDCC
2008
Springer
14 years 11 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
DATE
2004
IEEE
146views Hardware» more  DATE 2004»
15 years 1 months ago
Analyzing On-Chip Communication in a MPSoC Environment
This work focuses on communication architecture analysis for multi-processor Systems-on-Chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-proc...
Mirko Loghi, Federico Angiolini, Davide Bertozzi, ...
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
15 years 1 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
CORR
2010
Springer
94views Education» more  CORR 2010»
14 years 9 months ago
Unidirectional Error Correcting Codes for Memory Systems: A Comparative Study
In order to achieve fault tolerance, highly reliable system often require the ability to detect errors as soon as they occur and prevent the speared of erroneous information throu...
Muzhir Al-Ani, Qeethara Al-Shayea