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» Comparing memory systems for chip multiprocessors
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KDD
2008
ACM
186views Data Mining» more  KDD 2008»
16 years 2 days ago
Cut-and-stitch: efficient parallel learning of linear dynamical systems on smps
Multi-core processors with ever increasing number of cores per chip are becoming prevalent in modern parallel computing. Our goal is to make use of the multi-core as well as multi...
Lei Li, Wenjie Fu, Fan Guo, Todd C. Mowry, Christo...
94
Voted
LCTRTS
2004
Springer
15 years 5 months ago
Spinach: a liberty-based simulator for programmable network interface architectures
This paper presents Spinach, a new simulator toolset specifically designed to target programmable network interface architectures. Spinach models both system components that are ...
Paul Willmann, Michael Brogioli, Vijay S. Pai
85
Voted
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
15 years 5 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
IEEEPACT
2003
IEEE
15 years 5 months ago
Constraint Graph Analysis of Multithreaded Programs
This paper presents a framework for analyzing the performance of multithreaded programs using a model called a constraint graph. We review previous constraint graph definitions fo...
Harold W. Cain, Mikko H. Lipasti, Ravi Nair
PPOPP
2010
ACM
15 years 9 months ago
Is transactional programming actually easier?
Chip multi-processors (CMPs) have become ubiquitous, while tools that ease concurrent programming have not. The promise of increased performance for all applications through ever ...
Christopher J. Rossbach, Owen S. Hofmann, Emmett W...