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» Comparing memory systems for chip multiprocessors
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PPOPP
1997
ACM
15 years 1 months ago
LoPC: Modeling Contention in Parallel Algorithms
Parallel algorithm designers need computational models that take first order system costs into account, but are also simple enough to use in practice. This paper introduces the L...
Matthew Frank, Anant Agarwal, Mary K. Vernon
ANCS
2009
ACM
14 years 7 months ago
LaFA: lookahead finite automata for scalable regular expression detection
Although Regular Expressions (RegExes) have been widely used in network security applications, their inherent complexity often limits the total number of RegExes that can be detec...
Masanori Bando, N. Sertac Artan, H. Jonathan Chao
72
Voted
ISQED
2010
IEEE
176views Hardware» more  ISQED 2010»
14 years 8 months ago
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on...
Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dh...
117
Voted
RTAS
1997
IEEE
15 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
73
Voted
ICCSA
2007
Springer
15 years 3 months ago
FRASH: Hierarchical File System for FRAM and Flash
Abstract. In this work, we develop novel file system, FRASH, for byteaddressable NVRAM (FRAM[1]) and NAND Flash device. Byte addressable NVRAM and NAND Flash is typified by the DRA...
Eun-ki Kim, Hyungjong Shin, Byung-gil Jeon, Seokhe...