622 search results - page 52 / 125 » Comparing the Optimal Performance of Multiprocessor Architec... |
173
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MICRO
2007
IEEE
15 years 11 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
138
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CGO
2005
IEEE
15 years 11 months ago
2005
IEEE
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
146
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MICRO
2009
IEEE
15 years 12 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
146
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CORR
2006
Springer
15 years 5 months ago
2006
Springer
We consider a hybrid wireless sensor network with regular and transmit-only sensors. The transmit-only sensors do not have receiver circuit, hence are cheaper and less energy consu...
126
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WMPI
2004
ACM
15 years 10 months ago
2004
ACM
Abstract. Recent research indicates that prediction-based coherence optimizations offer substantial performance improvements for scientific applications in distributed shared memor...