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ITNG
2007
IEEE
15 years 4 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
ISCAS
2008
IEEE
287views Hardware» more  ISCAS 2008»
15 years 4 months ago
A high speed word level finite field multiplier using reordered normal basis
— Reordered normal basis is a certain permutation of a type II optimal normal basis. In this paper, a high speed design of a word level finite field multiplier using reordered ...
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad...
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
15 years 3 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
ICUMT
2009
14 years 7 months ago
On the architecture and the design of P2P live streaming system schedulers
-- In this paper we analyze P2P live streaming systems. Through this analysis we obtain the crucial parameters for their performance in terms of bandwidth utilization, set-up time,...
Athanasios Christakidis, Nikolaos Efthymiopoulos, ...
EUROSYS
2007
ACM
15 years 6 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek