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CF
2008
ACM
14 years 11 months ago
DMA-based prefetching for i/o-intensive workloads on the cell architecture
Recent advent of the asymmetric multi-core processors such as Cell Broadband Engine (Cell/BE) has popularized the use of heterogeneous architectures. A growing body of research is...
M. Mustafa Rafique, Ali Raza Butt, Dimitrios S. Ni...
DAC
2002
ACM
15 years 10 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
ICS
2005
Tsinghua U.
15 years 3 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
CGO
2003
IEEE
15 years 3 months ago
Compiler Optimization-Space Exploration
To meet the performance demands of modern architectures, compilers incorporate an everincreasing number of aggressive code transformations. Since most of these transformations are...
Spyridon Triantafyllis, Manish Vachharajani, Neil ...
CASES
2001
ACM
15 years 1 months ago
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
Girish Venkataramani, Walid A. Najjar, Fadi J. Kur...