1461 search results - page 101 / 293 » Comparing the Optimal Performance of Parallel Architectures |
FPL
2008
Springer
15 years 4 months ago
2008
Springer
The effectiveness of implementing bit-stream signal processing (BSSP) multiplier circuits in FPGAs, in terms of hardware resources and clock frequency, is presented. In particular...
137
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CCGRID
2010
IEEE
15 years 4 months ago
2010
IEEE
Idle desktops have been successfully used to run sequential and master-slave task parallel codes on a large scale in the context of volunteer computing. However, execution of messa...
119
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CASES
2009
ACM
15 years 9 months ago
2009
ACM
Embedded systems are often implemented on FPGA devices and 25% of the time [2] include a soft processor— a processor built using the FPGA reprogrammable fabric. Because of their...
160
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ICPP
2006
IEEE
15 years 9 months ago
2006
IEEE
— This paper focuses on the transfer of large data in SMP systems. Achieving good performance for intranode communication is critical for developing an efficient communication s...
131
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IPPS
2003
IEEE
15 years 8 months ago
2003
IEEE
Mesh partitioning is an important problem that has extensive applications in many areas. Multilevel algorithms are a successful class of optimization techniques which addresses th...