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» Comparing the Optimal Performance of Parallel Architectures
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ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 7 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
ICS
2005
Tsinghua U.
15 years 8 months ago
Think globally, search locally
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...
Kamen Yotov, Keshav Pingali, Paul Stodghill
ASAP
2006
IEEE
145views Hardware» more  ASAP 2006»
15 years 9 months ago
2D-VLIW: An Architecture Based on the Geometry of Computation
This work proposes a new architecture and execution model called 2D-VLIW. This architecture adopts an execution model based on large pieces of computation running over a matrix of...
Ricardo Santos, Rodolfo Azevedo, Guido Araujo
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 7 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
GECCO
2010
Springer
140views Optimization» more  GECCO 2010»
15 years 3 months ago
Shared memory genetic algorithms in a multi-agent context
In this paper we present a concurrent implementation of genetic algorithms designed for shared memory architectures intended to take advantage of multi-core processor platforms. O...
Dana Vrajitoru