1461 search results - page 110 / 293 » Comparing the Optimal Performance of Parallel Architectures |
133
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ICPP
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper, we present a hierarchical Data Cache Architecture called DCA to effectively slash local interconnect traffic and thus boost the storage server performance. DCA is ...
143
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MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
104
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DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
Sophisticated C compiler support for network processors (NPUs) is required to improve their usability and consequently, their acceptance in system design. Nonetheless, high-level ...
145
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MICRO
1997
IEEE
15 years 7 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
123
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HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
Processor architects have a challenging task of evaluating a large design space consisting of several interacting parameters and optimizations. In order to assist architects in ma...